1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to an EPROM (Erasable and electrically Programmable Read Only Memory) device which is used, for example, in an electronic computer and in which the threshold potential of each memory cell can be measured accurately and easily.
2. Description of the Prior Art
As illustrated in FIG. 1, a memory cell of an EPROM device comprises a source electrode 12, a drain electrode 14, a floating gate electrode 16, and a control gate electrode 18 which are formed on a semiconductor substrate 10. In the EPROM device, information "0" is written in by applying a high reverse-biased potential voltage to the drain junction in order to cause an avalanche breakdown therein and to inject hot electrons into the floating gate electrode 16 through an insulating layer 20. Information "1" is written, i.e., the information "0" in the memory cell is erased by radiating ultraviolet light into the memory cell, thereby dissipating the electrons stored in the floating gate electrode 16. When electrons are injected into the floating gate 16, i.e., when information "0" is stored in the memory cell, the electric field caused by the control gate 18 has little effect on the channel region between the source and the drain electrode, thereby resulting in a threshold potential Vth for the control gate 18 higher than that in the condition when information "1" is stored in the memory cell. For example, when electrons are injected into the floating gate 16, the threshold potential Vth is 10.0 V. When the electrons are not injected, the threshold potential Vth is 2.5 V. Therefore, during the readout of information, the potential of the control gate 18 is set to a value smaller than 10.0 V and larger than 2.5 V. Therefore, if electrons are injected into the floating gate 16, the memory cell transistor of FIG. 1 is turned off. If the electrons are not injected into the floating gate 16, the memory cell transistor remains in the turned on condition, this enables readout of information "1" or "0" stored in the memory cell.
The most important characteristics of the EPROM device are the magnitude of the threshold potential Vth and the stability of this magnitude. If the insulating resistance of the insulation layer 20 is not sufficiently large, the electrons stored in the floating gate electrode 16 are dissipated or the electrons are injected into the floating gate electrode 16 from the surroundings, whereby the magnitude of the threshold potential Vth is changed during, for example, readout of information from the memory cell or writing of information into adjacent memory cells or during changes in ambient temperature. A change of the threshold potential Vth of an EPROM cell beyond an acceptable range makes an EPROM cell unusable. To test whether the change of the threshold potential Vth is within the acceptable range, it is necessary to measure the magnitude of the threshold potential Vth.
FIG. 2 illustrates a schematic structure of a conventional EPROM device. In FIG. 2, W0, W1, . . . are word lines, i.e., row lines; B0, B1, . . . are bit lines, i.e., column lines; Q0, Q1, . . . are column selecting transistors; SA is a sense amplifier; RD is a row decoder; CD is a column decoder; and A0, A1, . . . and A5, A6, . . . are address bit signals. C00, C01, . . . are EPROM cells, each of which has the structure of FIG. 1 and each of which is disposed at the intersection of a word line and a bit line and connected therebetween. Conventionally, when measuring the threshold potential Vth of each of the memory cells, one of the memory cells, for example, C00, is selected by the row decoder RD and the column decoder CD and the power supply voltage to the EPROM device is changed. More particularly, the transistor Q0 is turned on so that the sense amplifier SA is connected to the memory cell C00, and the potential Vcc of the operating power source is changed from a low potential level to a high potential level so that the potential of the word line W0 changes gradually from the low potential level, e.g., OV, to the high potential level. Since the memory cell transistor C00 is in a turned-off condition at first, no current flows through the bit line B0. When the potential of the word line W0 is gradually increased and reaches a certain value, the cell transistor C00 is turned on and a current flows through the bit line B0. This current is detected by the sense amplifier SA, and a potential of the word line W0, i.e., a potential of the power source at the time the current of the bit line B0 is detected, becomes equal to the threshold potential Vth of the memory cell C00.
FIG. 3 illustrates a sense amplifier circuit SA used in the EPROM device of FIG. 2. The sense amplifier SA comprises a pre-sense circuit PS composed of transistors Q10 through Q15; a differential amplifier DA composed of transistors Q16 through Q21; and a reference voltage generator RG composed of transistors Q22 through Q26. The pre-sense circuit PS is connected to a memory cell Cij through a column selecting transistor Qj and a bit line Bj. The gate electrode of the memory cell Cij is connected to a word line Wi which is connected to a buffer section BUF of a row decoder. The reference voltage generator RG is connected to a dummy cell Cd whose gate electrode is connected to a power supply voltage Vcc.
In FIG. 3, the readout operation of the memory cell Cij is effected as follows: The potential of a point P3 of the buffer section BUF is changed to low and the potential of the gate electrode of the transistor Q31 is changed to high, so that the transistors Q28 and Q30 are turned off and the transistor Q31 is turned on. Therefore, the potential of the word line Wi becomes nearly as high as Vcc. The column-selecting transistor Qj is also turned on by a signal from a column decoder, so that the memory cell Cij is selected. A powerdown signal PD which is used to save power in the memory device is changed to high and the transistors Q12 and Q21 are turned on.
In this condition, if information stored in the memory cell Cij is "0", the memory cell Cij does not turn on, whereby the potential V1 of the gate electrode of transistor Q11 becomes relatively high and the potential V2 of the drain electrode of the transistor Q11, i.e., the potential of the gate electrodes of the transistors Q13 and Q15, becomes relatively low. Therefore, the transistors Q13 and Q15 are turned off and the potential of a sense signal SD becomes high, i.e., Vcc level. On the contrary, if the information stored in the memory cell Cij is "1", the potential of the sense signal SD becomes low, which is nearly equal to V1, e.g., 1 V. In this case, the reference voltage generator RG has substantially the same circuit structure as that of the pre-sense circuit PS except that the reference voltage generator RG does not have a transistor corresponding to the transistor Q12 of the pre-sense circuit PS. The resistance between the drain and the source electrode of the dummy cell transistor Cij is selected so that a reference voltage V.sub.REF generated from the reference voltage generator RG becomes a middle value between the high potential level and the low potential level of the sense signal SD when the power supply voltage Vcc is applied to the gate electrode thereof. Therefore, the change of the potential of the sense signal SD between a relatively high level and a relatively low level causes the differential amplifier DA to output a data output signal D which changes between low and high, respectively, and an inverted data output signal D thereof.
In the circuit of FIG. 3, the threshold potential Vth of the memory cell, e.g., Cij is measured by changing the potential Vcc of the power supply voltage in the readout mode, as mentioned before. As illustrated in FIG. 4, the potential of the sense signal SD falls in accordance with the potential rise of the power supply voltage Vcc. However, since the resistance between the drain and the source electrode of the dummy cell Cd changes according to the change of the potential Vcc, the reference voltage V.sub.REF generated by the reference voltage generator also changes in the same direction as illustrated in FIG. 4. Therefore, in a conventional EPROM device, it is impossible to measure the value of the threshold potential Vth accurately or to reduce the spread of the measured values of the threshold potential Vth of each of the memory cells.
Moreover, in a conventional EPROM device, the sequential measurement of the threshold potential Vth for every memory cell means that the time required for measuring the threshold potential Vth increases considerably with large memory capacities, i.e., when the number of memory cells is large, for example, 64K or 256K.